Memory systems integrated on semiconductor chips e.g., System-on-Chip (SoC) memory have commonly used two different power supply nodes for operation and storing of data therein. Such integrated circuit memory is often referred to as a dual-rail memory circuit. In such a dual-rail memory, the circuit will often use a first voltage supply rail for periphery circuitry (i.e., the I/O) provided by a first power supply node, and second voltage supply rail with a voltage provided by a second power supply node for the memory array. Having two different power supply nodes in a dual-rail memory is advantageous because one of the voltage supply nodes (the first supply node supplying voltage to the peripheral circuitry) may be reduced to zero volts or near zero volts during periods of non-use (e.g., sleep mode). However, the second supply voltage for the memory array is kept at the usual voltage level in order to maintain data stored in the memory cells. Another major advantage of the dual rail memory circuit is that it allows to reduce the voltage level of the first supply node thereby enabling low power modes.
Computing systems, therefore, may employ and overall power usage strategy for all circuits in the computing system. Thus, when the computing system enters into a sleep mode, a sleep signal may be conveyed to specific circuit blocks designated to enter into a power-saving mode via the sleep signal. Thus, a typical dual-rail memory is suited to utilize sleep mode by powering down the peripheral I/O circuitry when not in use. When exiting sleep mode, however, it is necessary to ensure that the first voltage supply node that supplies the peripheral I/O circuitry is ramped back up to the desired operating voltage level in a manner that ensures that data written to or read from the memory array will be accurately handled. Further, the same circuitry typically used for ensuring proper signal level of the first voltage rail should also function correctly during the first power-on event as well (e.g., restarting the entire computing system).